1. Technical Field
The present disclosure relates to a memory device, and more particularly, to a nonvolatile semiconductor memory device.
2. Discussion of the Related Art
In order to store more information in a memory device, the number of memory cells arranged in a matrix of intersecting word lines and bit lines is increased. A semiconductor memory chip of a 100 Mbit-class is commonly used and methods of its use tend to be varied and complex. Therefore, in order to efficiently utilize a main memory, operation management for the main memory may be performed. For example, information on software for a mapping operation of a memory map may be controlled. Information on hardware of a memory array may be modified due to a redundant configuration. These actions may be executed separate from user memory operations.
Therefore, condition data used to manage the main memory is stored in a management memory and is installed separately from the man memory. The condition data is protected from user manipulation. Also, since operation management for a memory is performed before a user performs an operation, management memory should be capable of operating at a high speed (relative to the read speed) without an operation error.
FIG. 4 is a circuit diagram of a conventional memory.
Referring to FIG. 4, four memory cells 1 through 4 forming 1 bit are formed in intersection points between four bit lines 5 through 8 and a word line 18, respectively. The four bit lines 5 through 8 are connected to source terminals of bit line select transistors 9 through 12, respectively. Drain terminals of the bit line select transistors 9 through 12 are connected to a source terminal of a bit line group select transistor 13. A gate terminal of the bit line group select transistor 13 and gate terminals of the bit line select transistors 9 through 12 are connected to a bit select circuit 15 through select lines 16 and 17, respectively, and a drain terminal of the bit line group select transistor 13 is connected to a read circuit 14-1.
The word line 18 is connected to a word driver 19, and dummy word lines 20 are connected to a Vss. Vss lines 21 are Vss lines of the memory cells and run in a word line direction. A coupling capacitance 22 between bit lines represents a line capacitance of adjacent bit lines between cell arrays forming 1 bit respectively. In FIG. 4, as the memory cells 1 through 4 form 1 bit, a plurality of bits are formed in one word line.
For example, when memory cells corresponding to 2 bits connected to read circuits 14-1 and 14-2 are read and selected by the bit select circuit 15 and the word driver 19, read signals of the memory cells 1 through 4 driven by the word driver 19 are input to the read circuit 14-1 through the bit line select transistors 9 through 12. The bit line group select transistor 13 is selected by the bit lines 5 through 8 and the bit select circuit 15 respectively. Similarly, read signals of the adjacent memory cells are input to the read circuit 14-2.
During a read operation, a read signal of the bit line 8 and a read signal of the adjacent bit line interfere with each other through the coupling capacitance 22 between bit lines, and thus input signals of the read circuits 14-1 and 14-2 affect each other as a noise. Therefore, due to a noise from the adjacent bit line, the plurality of memory cells may not be read at a sufficiently high read speed and operational error may not be adequately prevented. An example of a nonvolatile semiconductor memory device that seeks to prevent variation of one bit line from affecting other bit line is Japanese Patent Publication No. HEI9-245493.